YMTC Prepares a 9,600 MT/s 4F² Memory Prototype as Micron Questions the Architecture

YMTC is preparing a prototype of a memory cell architecture designed to work around limits associated with its lithography technology, according to Wccftech. The planned prototype is rated at 9,600 MT/s.

The report says YMTC is following CXMT, which is also pursuing the 4F² architecture. It describes the approach as a way for Chinese memory makers to address constraints linked to deep ultraviolet (DUV) lithography, amid restrictions on access to extreme ultraviolet (EUV) technology.

A 4F² memory cell uses one transistor and one capacitor, with the cell components arranged to reduce the area each cell occupies. The architecture is presented as a possible route to denser memory, though the excerpt does not give a capacity or production timeline for YMTC's prototype.

Micron, meanwhile, has called the miniaturization advantages attributed to 4F² a “myth,” Wccftech reports, and is pursuing 3D DRAM. The opposing approaches reflect a broader technical question: whether memory makers can gain practical density improvements from the 4F² design under their manufacturing constraints.

The 9,600 MT/s figure is a stated operating rate for the prototype; the available source excerpt does not establish that it is a shipping product or confirm its commercial availability.