Cadence Secures TSMC A14 Tool Certification, Reports 2.5X Fewer Design Iterations

Cadence has expanded its collaboration with TSMC through tool certification for TSMC’s A14 process technology, according to an announcement summarized by Wccftech.

The partnership is intended to support agentic AI chip and 3D-IC design flows across TSMC’s N3, N2, A16, A14 and 3DFabric processes. Cadence also announced a UALink solution demonstrated in TSMC N3P and new silicon-proven IP for N3P and N2P technologies.

Wccftech’s headline says the certification cuts design iterations by 2.5X. The source describes the work as part of an expanded effort to provide advanced capabilities for AI and HPC designers.

The announcement links Cadence’s tools and IP with several TSMC process technologies, covering both conventional chip designs and 3D-IC development. It does not provide additional details in the supplied material about the certification timeline, specific products using the IP, or customer deployments.